Why does the Quartus II software convert my bidirectional pin to an output-only pin?

Description

The Quartus® II software version 6.0 and later synthesizes VHDL directional signals more strictly. Because it enforces the VHDL rules, the Quartus II software converts incorrectly-coded bidirectional buffers to output pins.

For example, if you implement a bidirectional buffer as shown in the following code, the Quartus II software synthesizes an output pin (beginning with version 6.0).

process(mdio_out,mdio_oe)
begin
    if (mdio_oe = '1') then
        mac_mdio <= mdio_out;
    else
        mac_mdio <= 'Z';
    end if
end process;

mdio_oe <= NOT(mdio_oe_n);
test_out <= mac_mdio and test;
mii_mdio <= mac_mdio;

If mac_mdio is a signal and mii_mdio is the bidirectional port, the last assignment above is directional. As written, it is impossible for data to flow from mii_mdio to mac_mdio. Beginning with version 6.0, the Quartus II software enforces the directional nature of this VHDL assignment by inserting a buffer between mac_mdio and mii_mdio. This buffer appears in the RTL Viewer as a directional buffer in series with the tri-state buffer, and the intended bidirectional pin (mii_mdio) is synthesized as an output only.

Earlier versions of the Quartus II software do not enforce the directional nature of these types of assignments, synthesizing the code above as a bidirectional pin.

To conform to the VHDL standard, remove the last signal assignment statement in the example above and write the code as follows:

process(mdio_out,mdio_oe)
begin
    if (mdio_oe = '1') then
        mii_mdio <= mdio_out;
    else
        mii_mdio <= 'Z';
    end if;
end process;

mdio_oe <= NOT(mdio_oe_n);
test_out <= mii_mdio and test;