Why does the O-RAN FPGA IP have a missing IQ sample and asserted error register after processing a valid U-Plane data packet through the receiver transport interface?

Description

Due to a problem in the O-RAN FPGA IP version 1.9.1 and earlier, you may see the O-RAN FPGA IP had a missing IQ sample and asserted error register after processing valid U-Plane data packet through the receiver transport interface.

Resolution

This problem is fixed in the 2.0.0 version of the O-RAN FPGA IP Webcore.