Why does the Multi Channel DMA FPGA IP for PCI Express* Design Example for F-Tile variant fail to simulate when using the Cadence Xcelium* simulator?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 22.1 to 23.3, the Multi Channel DMA FPGA IP for PCI Express* Design Example for F-Tile variant fails to simulate when using the Cadence Xcelium* simulator.

Resolution

To work around this problem in simulation,  use the below command to run with the Cadence Xcelium simulation:

For Quartus® Prime Pro Edition Software version 23.3

sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sv" USER_DEFINED_ELAB_OPTIONS="-warn_multiple_driver\ -timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log

For the Quartus® Prime Pro Edition Software version 22.1 to 23.2

sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sv" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log

This problem is fixed in Quartus® Prime Pro Edition Software version 23.4.