Why does the ModelSim*-Intel® FPGA software simulator generate an error while simulating the Intel Agilex® 7 FPGA EMIF IP design example with an Efficiency monitor enabled?

Description

While running the register transfer level (RTL) simulation for the Intel Agilex® FPGA EMIF IP design example with Efficiency monitor enabled, errors occur with the following error message: 

Error (vsim-8604)   ../ip/ed_sim/ed_sim_dut/altera_amm_effmon_191/sim/altera_amm_effmon_single_top.sv(246): NaN (not a number) resulted from a division operation 

Resolution

This issue has been fixed in the Intel® Quartus® Prime Pro Edition Software version 21.2 or later versions.