Why does the Memory Subsystem FPGA IP fail while generating the example design?

Description

Due to a problem in the Quartus® Prime Pro Edition Software, you might see the following error when generating an example design for the Memory Subsystem FPGA IP v1.0.0

"mem_ss_0: An error has occurred when generating the sim example design fileset. See sim/make_sim_design.log for details"

This IP is still under development and is not recommended for design or simulation.

Resolution

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.3.