Why does the LTSSM of the GTS AXI Streaming FPGA IP for PCI Express* remain at the Polling.Compliance state after reconfiguring the Agilex™ 5 FPGA E-Series 065B Development Kit?

Description

The Agilex™ 5 FPGA E-Series 065B Modular Development Kit implements eight PCIe* lanes on the edge connector. Only the lower four lanes are used, while the upper four are properly terminated but unused. The presence of the termination at the upper four unused lanes can lead to complications at the root port during reconfiguration.

Resolution

To work around this problem, you can either configure the PCIe* link width to x4 in the host system BIOS or apply insulating tape to mask the upper four lanes.