Why does the IO Bank Usage report in the Quartus® Prime Pro Edition Software show that a VREF is required for banks with Differential SSTL/HSTL inputs when using Stratix® 10 FPGA devices?

Description

Due to a problem in Quartus® Prime Pro Edition Software version 24.1 and earlier, when using Stratix® 10 FPGA devices, the IO Bank usage shows that a VREF is required for banks that contain Differential SSTL/HSTL inputs but no single-ended SSTL/HSTL inputs. 

Resolution

Differential SSTL/HSTL inputs do not require an external VREF so that you can ignore this for banks with Differential SSTL/HSTL inputs and no single-ended SSTL/HSTL inputs.

This issue is fixed starting in Quartus® Prime Pro Edition Software version 24.3.