Why does the Intel FPGA VIP Suite Mixer II IP lockup for certain maximum output frame width?

Description

Due to a problem with the the Mixer II IP in Quartus® Prime software version 16.1, the Mixer II IP may lock up during operation if the IP is configured with "Maximum output frame width" which is an exact power of 2, for example, 4096, 2048, 1024 and etc.

Resolution

This problem has been fixed in Quartus® Prime software version 17.0.