Why does the Intel Agilex® FPGA EMIF fail timing when Traffic Generator and ECC are enabled in Intel® Quartus® Prime Pro Edition Software version 20.3?

Description

 Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3, you may encounter timing failures in the Intel Agilex® FPGA DDR4 IP when Traffic Generator and ECC are both enabled.

 

 

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3 onwards.