Why does the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* with Avalon® Memory Mapped (Avalon-MM) DMA interface generated example design encounter fatal error in simulation?

Description

Due to a problem with the Intel® Quartus® Prime software version 19.3 and earlier, you may encounter the above problem when simulating the example design generated from the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* with Avalon® Memory Mapped (Avalon-MM) DMA interface and Gen2 mode in Modelsim* Intel® FPGA Starter Edition.   

Resolution

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.4.