Why does the Intel® Arria® 10 or Intel® Cyclone® 10 Avalon®-MM DMA 128-bit interface for PCIe* issue warnings about DMA master cannot safely write to DTS slave?

Description

The Intel® Arria® 10 or Intel® Cyclone® 10 Avalon®-MM DMA 128-bit interface PCIe* example design creates two warnings:

Warning: pcie_example_design.DUT.dma_rd_master/DUT.rd_dts_slave: Master DUT.dma_rd_master cannot safely write to slave DUT.rd_dts_slave, because the master data width is narrower than the slave data width. Add byteenable support to the slave to support safe writes from a narrow master.

Warning: pcie_example_design.DUT.dma_rd_master/DUT.wr_dts_slave: Master DUT.dma_rd_master cannot safely write to slave DUT.wr_dts_slave, because the master data width is narrower than the slave data width. Add byteenable support to the slave to support safe writes from a narrow master.

Resolution

Absence of byte enable in the slave DTS 256-bit interface does not cause functional issue with the master DMA 128-bit core. The DMA controller always requests an even number of 128-bit words to the host.  When completion data returns, the IP logic combines the low and high 128-bit data forming 256-bit data before sending to the DTS.  Therefore, using byte enable masking is not needed.

These warnings can be safely ignored.

This problem is not going to be fixed in any future Intel® Quartus® Prime software release.