Why does the Intel® Stratix® 10 Avalon®-ST PCI Express* Hard IP for H-Tile devices with Multifunction enabled generate RTL with max_read_req_size parameter for PF2 and PF3 set to 0?

Description

Due to a problem with the Intel® Quartus® Prime Pro version 18.0, the Intel® Stratix® 10 Avalon®-ST PCI Express* Hard IP for H-Tile devices with Multifunction enabled generates RTL with the max_read_req_size parameter for PF2 and PF3 set to 0 instead of 2 as specified by PCIe* specification.

Resolution

This problem is fixed in Intel® Quartus® Prime Pro version 18.1.