Why does the High Speed Reed Solomon FPGA IP Core generate an incorrect set of check symbols for my data?

Description

Due to a problem with the RTL source generation of the High Speed Reed Solomon FPGA IP Core, if the 'Hyper-optimization' parameter is set to 'High' the IP will generate an incorrect set of check symbols for the incoming data payload.
 

Resolution

To work around this problem, set the 'Hyper-optimization' parameter to 'Low'.