Why does the GTS Serial Lite IV IP design example fail VHDL simulation using the Riviera-PRO™ simulator?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, you will observe the GTS Serial Lite IV IP design example fail VHDL simulation using the Riviera-PRO simulator.

Resolution

To work around the above problem, you can apply either of the following methods:

1. Perform Verilog simulation, or
2. Use a different simulator.