Why does the generation of the F-Tile DisplayPort FPGA IP Design Example with the simulation option enabled fail?

Description

Due to a problem in the Quartus® Prime Pro Edition Software v23.4 and earlier, the F-Tile DisplayPort FPGA IP Design Example with simulation enabled cannot be generated successfully.

Resolution

Do not select the simulation option when generating the F-Tile DisplayPort FPGA IP Design Example. The design example can be generated successfully without the simulation option. 

This problem has been fixed starting in version 24.1 of the Quartus® Prime Pro Edition Software.