Why does the F-Tile Serial Lite IV IP Deterministic Latency Design Example fail Simulation in the Quartus® Prime Pro Edition Software version 25.1?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you might fail the simulation for the F-tile Serial Lite IV IP Example Design if you performed the following during example design generation:

• Choose "Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile)" or "Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 2 4x F-Tile)" for the "Select Board" parameter in the Example Design Tab

Resolution

To work around the above problem, you can perform the following during example design generation:

• Choose "No Development Kit" for the "Select Board" parameter in the Example Design Tab

This problem was fixed starting with version 25.1.1 of the Quartus Prime Pro Edition Software.