Why does the F-Tile SDI II Intel® FPGA IP simulation fail and result in no video displayed on hardware when receiving SD-SDI video standard in the Intel® Quartus® Prime Pro Edition Software version 23.2?

Description

Due to changes of enable_port_control_of_cdr_ltr_ltd=Enable and lock-to-reference (LTR) mode in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP,  you may see the F-Tile SDI II Intel® FPGA IP simulation will fail with SD-SDI video standard that will result in no video displayed on hardware when receiving SD-SDI video standard in the Intel® Quartus® Prime Pro Edition Software version 23.2.

Resolution

To work around this problem, add the following line in the Quartus Settings File (QSF):

set_instance_assignment -name HSSI_PARAMETER "enable_port_control_of_cdr_ltr_ltd=DISABLE" -to <rx_serial_pin_name>

 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 23.3.