Why does the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP in simulation fail to assert the tx/rx_reset_ack signal?

Description

The F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Version: 2022.09.26 and earlier is missing the simulation clock requirement for the Nios® CPU Subsystem. 

If the frequency range provided in Table 7. Clock Signals are followed for the i_cpu_clk input; the IP in the simulation will fail to assert the tx/rx_reset_ack after tx/rx_reset is asserted.

• 100 to 250 MHz frequency when Enable ECC protection is disabled.
• 100 to 200 MHz frequency when Enable ECC protection is enabled.

Resolution

For simulation only, connect the i_cpu_clk pin of the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP to a 100GHz clock. This will speed up F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP simulation, and tx/rx_reset_ack will be asserted correctly.

There is no planned hardware fix for this problem. The User Guide mentions the simulation clock signals requirement.