Why does the F-Tile HDMI IP TX-Only AXIS-VVP Full design not working for FRL Rate 0 to 5?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile HDMI IP Agilex™ 7 FPGA TX Only Design (AXIS-VVP Full, CLOCKS_ARE_SAME = 1) will have display issues when the FRL Rate is not set to 6, including the TMDS variant.

Resolution

To work around this problem, ensure that the option in "IP GUI >> Advance configuration >> Video in and out use the same clock" is not enabled when generating the TX-Only Design.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.