Why does the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express fail to be enumerated after loading the FPGA programming file?

Description

The F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express might fail to be enumerated after loading the FPGA programming file due to the FPGA image configuration time exceeding the PCI Express 100 ms power-up-to-active time requirement.

Resolution

To work around this problem, re-enumerate the PCI Express link once the FPGA is successfully configured, or pause the PC boot process until the FPGA is configured. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.