Why does the EDA netlist writer not create a valid netlist for gate-level simulation of the V-Series 28 nm Hard IP for PCI Express MegaCore Function?

Description

The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 14.1.