Why does the DSP block fail to be fully registered?

Description

In the Intel® Quartus® Prime Pro Edition Software version 18.1 and earlier, you might see the registers cannot be packed to the DSP block when using signal declarations with non-zero left-most range and without explicit initialization.

SIGNAl a: integer RANGE -32768 to 32768;

This register is initialized to its left-most value, which is -32768 so the most significant bit of the register has power-up=1 and cannot be packed to the DSP block.

Resolution

To work around the problem, an explicit initialization value of 0 has to be added to the declaration.

SIGNAl a: integer RANGE -32768 to 32768 := 0;