Why does the Design Closure Summary fail in the Agilex® 7 FPGA HDMI IP Example Designs after changing the Layout Options under the IP GUI ?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may observe the Design Closure Summary including Timing Closure marked as Fail in the Agilex® 7 FPGA F-Tile HDMI IP Design Example. Additionally, you may notice that the pll_frl_rx_outclk0 frequency is flagged as extremely high. This problem occurs when you change the “Layout Options” from its default values into any other value in the IP GUI.

 

Resolution

To work around this problem, follow the steps below:

1. go to "project" tab at Quartus -> Clean Project

2. locate directory rtl/ip/nios/nios_intel_hdmi_rx_phy/intel_hdmi_rx_phy_103/synth/nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v

• • The filename nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v may vary for each generated design.
  • Please verify files that start with nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103 (for example: nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxx.v).

     

 

3. Change the line #153 from [TMDS_1_GREEN_TRANSCEIVER_21] into [0]

4. Click saves and re-run the full compilation.

This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.