Why does the Debug Toolkit of the Agilex™ 7 FPGA R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP report transaction timeout in the Quartus® Prime Pro Edition Software Version 23.3?

Description

Due to a problem in Quartus® Prime Pro Edition Software version 23.3, you might observe the error message shown below when launching the Debug Toolkit of the Agilex™ 7 FPGA R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP.

master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.

Resolution

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.4.