Why does the Altera PLL IP signal phase_done not assert in gate-level simulation of dynamic phase shift?

Description

Due to a problem in the Quartus® II software version 15.0.2 and earlier, phase_done may not assert after a phase shift by phase_en pulse in the gate-level simulation of dynamic phase shift with Altera PLL IP.

This problem affects simulation only. 

Resolution

This problem is fixed in the Intel® Quartus® Prime Standard Software version 16.0

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