Why does the 2D-FIR II (4K ready) FPGA IP core return unexpected data between two output samples in simulation when using the SIEMENS* QuestaSim*?

Description

Due to a problem with the encryption of the 2D-FIR II (4K ready) FPGA IP simulation files for the SIEMENS* QuestaSim*, unknown data will be seen between two consecutive output data when simulating the 2D-FIR II (4K ready) FPGA IP.

This issue does not affect the operation in hardware.

Resolution

No workaround for this simulation problem exists.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

Updated 3 months ago

Version 2.0

agilex™ 7 fpgas and socs

arria® 10 fpgas and socs

arria® ii fpgas

arria® v fpgas and socs

cyclone® iv fpgas

cyclone® v fpgas and socs

max® 10 fpgas

stratix® 10 fpgas and socs

stratix® iv fpgas

stratix® v fpgas

Knowledge Base Article

Why does the 2D-FIR II (4K ready) FPGA IP core return unexpected data between two output samples in simulation when using the SIEMENS* QuestaSim*?

Description

Resolution