Why does Stratix V PLL simulation show that output clocks run at the frequency defined in the megafunction regardless of the input reference clock frequency?

Description

Due to a problem in the Quartus® II software version 11.0, simulation of PLLs in Stratix® V devices always shows the same output clock frequencies regardless of the frequency of the reference clock.

This problem has been fixed beginning with the Quartus II software version 11.0 SP1, in which the simulation displays a warning because the reference clock signal does not have the specified period. However, the output clock frequency adjusts to the frequency of the reference clock signal.

Resolution