Why does simulation of the JESD204B IP Core fail when the "Enable Control and Status Registers" transceiver option is enabled?

Description

When you enable the Enable Control and Status Registers transceiver option in the JESD204B Intel® FPGA IP, the intellectual property (IP) core simulation will fail as the transceiver will be stucked at reset. You might observe in simulation that the tx_serial_data/rx_serial_data signals, or the xcvr_rst_tx_ready/xcvr_rst_rx_ready signals are stucked at 0.

This problem affects  the JESD204B Intel FPGA IP generated for Intel® Arria® 10 and Intel® Stratix® 10 devices in the Intel® Quartus® Prime Standard and Pro Edition Software versions 17.0 or earlier.

Resolution

To work around this problem, supply a 100 MHz - 125 MHz clock to the reconfig_clk port, and define a reset sequence to the reconfig_reset port.

Alternatively, turn off the transceiver reconfiguration options. Note that the IP core testbench does not perform any operations on the transceiver reconfiguration interface.

This problem is fixed starting from the Intel Quartus Prime Software versions 17.0.1.