Why does simulation fail when using the Interlaken design example?

Description

Due to a problem in the Interlaken IP Core (2nd Generation), the rx_digitalreset and reset_stat keep toggling when using the modelsim or ncsim simulation environment. As a result, the simulating system can't enter lock status or finish successfully.

Resolution

This problem does not exist when using the VCS simulation environment.

This problem has been fixed starting in version v17.1 of the Intel® Quartus® Prime software.