Why does reconfiguration of Intel® Stratix® 10 devices fail with designs containing an instance of any of the SDM Mailbox IPs?

Description

Due to a known problem in the Intel® Quartus® Prime Pro Edition Software v18.1 Update 1 and later, while attempting to reconfigure an Intel® Stratix® 10 device via any of the supported configuration methods, including Configuration via Protocol (CvP),  you may see the device gets stuck and requires a power cycle to recover.

This may be seen if the design uses the Intel® Stratix® 10 FPGA Mailbox Client IP commands on its own for accessing the Intel® Stratix® 10 FPGA Secure Device Manager peripherals or via the following software intellectual property (IP) cores such as:

• Intel® Stratix® 10 FPGA Temperature Sensor
• Intel® Stratix® 10 FPGA Voltage Sensor
• Chip ID Intel® Stratix® 10 FPGA IP core
• Intel® Stratix® 10 FPGA Serial Flash Mailbox Client Intel FPGA IP core
• Intel Stratix 10 FPGA Partial Reconfiguration Controller IP core or HPS cold resets on Intel Stratix 10 FPGA Hard Processor System. 

Resolution

To resolve this problem, update the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software 21.1/21.2/21.3/21.4/22.1/22.2/22.3. 

 

The latest device manager firmware versions are available from the following link: 

What is the latest device firmware for Intel® Agilex™ and Intel® Stratix® 10 devices?