Why does reconfiguration of Intel® Stratix® 10 MX devices fail when the hbm_only_reset_in port of High Bandwidth Memory (HBM2) Interface Intel® FPGA IP is connected to the output of Intel® FPGA Reset Release FPGA IP or other core logic?

Description

When using Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, performing reconfiguration of Intel® Stratix® 10 MX devices in user mode will fail if the hbm_only_reset_in port for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP is connected to the output of Intel® FPGA Reset Release FPGA IP or other core logic.

During reconfiguration, if the hbm_only_reset_in is driven with logic value 1'b1, then the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP will always be in a reset state and result in configuration failure.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2.

To resolve this problem, update the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software  21.2/21.3/21.4/22.1/22.2/22.3. 

 

The latest device manager firmware versions are available from the following link: 

What is the latest device firmware for Intel® Agilex™ and Intel® Stratix® 10 devices?