Why does Qsys generation fail for the Nios II Gen2 processor when using VHDL?

Description

Due to a problem with the Quartus® II software version 14.0 and later, Qsys systems that include the Nios II Gen2 processor fail to generate VHDL simulation models and testbenches.

Resolution

To work around this problem, generate the simulation model and testbench in Verilog HDL.

This problem is fixed beginning with version 15.0 of the Quartus II software.