Why does preforming read and write data via FPGA to HPS bridge fail when SMMU is enabled in HPS IP?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 release and earlier, the Agilex™ 5 HPS FPGA to HPS bridge could not be accessed by the FPGA Fabric when SMMU is enabled.

Resolution

This problem is resolved in Quartus® Prime Pro Edition Software v24.3.1.