Why does my VHDL array slice assignment inside of a loop not give the expected simulation result?

Description

If you assign an array slice using a loop and assign other elements in a different process then you may see that the elements assigned outside of the loop result in 'X' or 'U' in order to comply with the VHDL standard.

This simulation result may occur because the simulator is required to create drivers for the longest static prefix of the signal. This means that as the array is indexed using a variable the simulator is required to create drivers for every element of the array.

Resolution

To avoid this simulation behavior, only assign values to an array in the same process as the loop.

For more information on how drivers are associated with signal assignments, see VHDL IEEE standard 1076-1987, section 9.2.1 or 1076-1993, section 12.6.1.