Why does my third-party PCI Express BFM report an error for TX EIOS to Electrical Idle (TTX-IDLE-SET-TO-IDLE) timing violation?

Description

When simulating the Altera® Hard IP for PCI Express® as endpoints with third-party BFMs, a simulation error may be reported for the time between sending out EIOS and entering Electrical Idle.

An example Denali BFM error for this case is shown below:

*Denali* Error: <sword_tb.ep1>@42853200 ps :: Detected[cfg_0_0] (TX) [] PL_TTX_IDLE_SET_TO_IDLE [PCISIG].  [port_0].TX: Transmitter exceeded TTX-IDLE-SET-TO-IDLE (20 Gen1-UI).

This issue only affects simulation and has no impact on hardware.

The root cause is due to transciever simulation model analog PMA timing inaccuracies.

Resolution

Modify the file altera_xcvr_fpll_a10.sv to add a timescale as shown below:

ifdef ALTERA_RESERVED_QIS_ES

.pipe12_elec_idle_delay_val  (3\'b100),

endif

3. Save and recompile your simulation