Why does my Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation hang in the reset state?

Description

Your Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation may hang in the reset state if you have not applied a Power On Reset (POR) pulse to the reconfig_reset signal of the Avalon Memory Mapped (AVMM) reconfiguration interface.

Resolution

To work around this problem, you can apply a two reconfig_clk cycle pulse to the reconfig_reset signal at the start of your RTL simulation.