Why does my PCI Express Gen3 simulation down train to x1 link width?

Description

Due to a known issue, the PCIe® link downtrains to Gen3x1 when simulating  Arria® V GZ or Stratix® V devices using the Altera® bus functional models (BFM).

Resolution

As a workaround for simulation only, disable "Enable adaptive equalization (AEQ) block" option within the Transceiver Reconfiguration Controller Megafunction.