Why does my HPS design fail Analysis & Synthesis but report zero errors?

Description

Due to a problem in the Quartus II software version 12.1, you may see Analysis & Synthesis fail by report zero errors if you have not connected your Hard Processor System (HPS) directly to FPGA pins. HPS I/O must be connected to pins without any intervening logic.

Resolution

To work around this problem, make sure the HPS I/O are connected directly to FPGA pins.

Future releases of the Quartus II software will give an error message for this incorrect connection.