Why does my Avalon Memory Mapped bus hang when accessing the transceiver reconfiguration controller in Arria V, Cyclone V and Stratix V devices?

Description

Avalon® Memory Mapped accesses to the transceiver reconfiguration controller in the Arria® V, Cyclone® V, and Stratix® V, devices will hang if the accesses are made to addresses outside of the specified address space of Table 16-8 of the Altera Transceiver Phy IP Core User Guide.

http://www.altera.com/literature/ug/xcvr_user_guide.pdf