Why does my Arria 10 SoC  pre-producion (ES) device fail to boot after a HPS reset with the IOPLL soft fix enabled?

Description

In designs targeting pre-production Arria® 10 SoC devices (ES, ES2) with the IOPLL soft fix enabled, the SDRAM L3 Interconnect in the Hard Processor System (HPS) can become corrupted after a cold or warm HPS reset and result in incomplete transactions when accessing HPS-connected external SDRAM or memory mapped registers in the SDRAM L3 Interconnect. 

This issue is very intermittent in nature and has only been observed to occur after a large number of HPS reset cycles when the Arria 10 External Memory Interfaces for HPS IP instance’s global_reset_n input is asserted by an HPS reset output.  Once corrupted, an access to the SDRAM L3 Interconnect by any master in the HPS or FPGA portion of the SoC can cause the interconnect to lock up.  Symptoms include HPS boot intermittently halting immediately after U-Boot console indication of FPGA configuration completion or HPS SDRAM calibration success.

Resolution

To recover from the lock up condition, the SDRAM L3 Interconnect must be reset.  If the lock up results from an HPS master access, the entire HPS must be cold or warm reset to recover, otherwise it may be possible to reset the interconnect under software control using the brgmodrst.ddrsch register bit in the Reset Manager in the HPS.

This issue can be avoided by permanently connecting the HPS EMIF IP instance’s global_reset_n input to its inactive logic high state.  If this is not compatible with your application, contact Altera for further assistance and a reset sequencing workaround for your application.

Note:  This issue only effects pre-production (ES ES2) Arria 10 SoC devices when the IOPLL erratum soft fix is enabled.  This issue does not effect in production devices.