Why does my Arria 10 HPS EMAC to FPGA interface not function correctly in hardware?

Description

Due to a problem in the Quartus® II software versions 15.0 Update 2 and earlier there is a missing clock assignment for the clock(s) used to launch the data from the HPS EMAC core(s) into the core of the FPGA.
As a result these HPS EMAC to FPGA paths will not be timing analysed.

Resolution

To correct this you should manually create the following clock assignments:

For EMAC0:

create_clock -name EMAC_TX_CLK -period 8.00 [get_keepers {*|fpga_interfaces|peripheral_emac0~phy_txclk0_cmrefclk.reg__nff}]

For EMAC1:

create_clock -name EMAC_TX_CLK -period 8.00 [get_keepers {*|fpga_interfaces|peripheral_emac1~phy_txclk0_cmrefclk.reg__nff}]

This problem is scheduled to be resolved in a future release of the Quartus II software.