Why does Mentor* ModelSim* simulation of the eSRAM Intel® FPGA IP generate X in the waveform?

Description

In the Modelsim* SE 2020 version software, you may see 'X' in the simulation of the eSRAM Intel® FPGA IP due to an encrypted code problem in the simulator.

Resolution

To work around this problem, run the simulation with the prior Modelsim* SE 2020 (e.g., Modelsim SE 2019.2) version. 

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.