Why does marginal degradation of 1.8V VIL I/O standard occur on Stratix® 10 FPGAs and Agilex™ FPGAs family SDM I/O pins after long-term operation?

Description

On all Stratix® 10 FPGA and Agilex™ FPGA devices, when the board MSEL is set to JTAG but Quartus® Prime design software is configured to AS or AVST×8, and SDM I/O pins are left unconnected (NC), long-term operation may cause the 1.8V VIL on those SDM I/O pins to degrade below the datasheet specification of 0.5985V (0.35 × 1.71V). Refer to device datasheet under Single-Ended I/O Standards Specifications section for SDM IO I/O standard specification. The degradation can lead to configuration issues.

Resolution

Select AVST×16 as the configuration scheme in Quartus when using JTAG MSEL with all SDM I/O pins left unconnected. AVST×16 does not use any SDM I/O pins, preventing the degradation. Refer to Configuration User Guide for the steps to enable dual-purpose pins when setting AVSTx16 mode in Quartus.

Starting in Quartus® Prime Pro edition software version 26.1, a note will be updated in the Configuration User Guide and the tooltips for the Configuration scheme category under Device and Pin Options in Quartus.