Why does link-up fail after a Root Complex power cycle when using the P-Tile Intel® FPGA IP for PCI Express* in Endpoint or Upstream Port configuration with the Intel® Quartus® Prime Pro Edition Software version 22.1?

Description

Due to a problem in P-Tile Intel® FPGA IP for PCI Express* with the Intel® Quartus® Prime Pro Edition Software version 22.1, link-up failure will occur after a Root Complex power cycle when using the common clock scheme as Endpoint or Upstream Port mode. 

Resolution

To work around this problem when using the Intel® Quartus® Prime Pro Edition Software version 22.1, implement a separate clock scheme.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3.