Why does generation of the DisplayPort Intel® FPGA IP UHBR10 (Ultra High Bit Rate 10) design example fail?

Description

When generating the DisplayPort Intel® FPGA IP UHBR10 (Ultra High Bit Rate 10) design example, the following error messages might be observed when the TX/RX Maximum link rate is set to 10 Gbps.

Error: dp_0: Neither "Simulation" nor "Synthesis" check boxes from "Files Types Generated" are selected to allow generation of Design Example Files.

Resolution

 To successfully generate the DisplayPort Intel® FPGA IP UHBR10 design example, turn on the Enable Video input Image port parameter.