Why does elaboration of the JESD204B Intel® FPGA IP Nios® control design example fail, with a setting of L=1?

Description

Elaboration of an Intel® Arria® 10 FPGA JESD204B Nios® control design example with L=1 may fail in the Intel® Quartus® Prime Standard Edition Software v17.0 due to a problem with the Platform Designer interconnect with the reconfig_* interface, resulting in the Platform Designer not generating the source code files.

Other JESD204B Intel FPGA IP design example variants, including Nios control with L>1, RTL state machine control, generic Nios control, and generic RTL state machine control are not affected by this problem.

Resolution

To work around this problem, follow these steps:

1. Locate and back up a copy of the following TCL file in your Intel Quartus Prime Software installation directory:
   ip/altera/altera_jesd204/src/lib/phy_adapter/altera_jesd204_phy_adapter_xs_hw.tcl
2. Open the TCL file with text editor. Search for procedure xseries_avmm_adapter.
3. Add $d_L == 1 OR condition check into the if statement below in the xseries_avmm_adapter procedure. There will be three occurrences of the if statements in the procedure:

   Before the change:

   if {[param_is_true RECONFIG_SHARED]

   After the change:

   if {[param_is_true RECONFIG_SHARED || $d_L == 1}

4. Save the modified TCL file.
5. Re-launch the Intel Quartus Prime Software, create a new project or re-open an existing project, and generate the Intel Arria 10  FPGA JESD204B design example.

This problem is fixed starting from the Intel Quartus Prime Software v17.0.1.