Why does Design Assistant report the D102 warning for a clock transfer inside the Nios II processor?

Description

Due to a problem in the Quartus® II software version 11.0 and later, the Design Assistant may report a D102 warning for a clock transfer inside Nios® II processor when JTAG Debug Module is enabled. D102 gives the warning message "Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain". The source node name is for this violation is *_jtag_debug_module_tck|sr, and the source clock name is altera_reserved_tck.

Resolution

This warning can safely be ignored.