Why does Design Assistant not report a rule violation when my design uses a PLL locked signal as an asynchronous reset signal?

Description

Due to a problem in the Quartus® II software version 13.1 and earlier, Design Assistant does not report a rule violation when the locked signal of a PLL is connected directly to the asynchronous reset of a register.

When using the locked signal of a PLL as a reset, synchronize the signal to the destination clock domain to ensure correct timing analysis.

Resolution

This problem is scheduled to be fixed in the future release of the Quartus II software.