Why does avl_ready deassert after avl_write_req is asserted in my DDR3 and DDR2 SDRAM High Performance Controller II IP?

Description

When error correction code (ECC) is enabled, you will see avl_ready de-assert after avl_write_req is asserted increasing the Write latency. It is because the controller needs to wait for incoming data (deassert ready signal) and then decide if read-modify-write operation is required during command loading.

Resolution

This behavior will not occur if ECC is disabled.

This problem is fixed starting with the Quartus® II software version 12.0.