Why does an AXI-Lite non-word-aligned register access to the PTP packet classifier within the Ethernet Subsystem Intel® FPGA IP fail to function properly?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, non-word-aligned register accesses to the PTP packet classifier within the Ethernet Subsystem Intel® FPGA IP will fail to complete properly. 

Resolution

There is no workaround for this problem. You should ensure that all register accesses to the packet classifier are performed to word-aligned addresses.
This problem has been fixed in version 23.2 of the Intel® Quartus® Prime Pro Edition Software.